SOI technology employs a layer of semiconductor material formed over an insulating layer on a supporting bulk wafer. The structure can be formed by different well-known techniques in the art, for example, separation by implanted oxygen, bonding and etching back, and zone melting and recrystallization, among others. Typically, the structure includes a film of monocrystalline silicon (herein referred to as the upper semiconductor layer) formed on a buried layer of silicon dioxide, which in turn is formed on a monocrystalline silicon substrate.
Field effect transistors (FETs) are typically fabricated in the upper semiconductor layer of an SOI structure. In a FET device on an SOI substrate, a conductive path is established within the upper semiconductor layer between two regions of the same conductivity type, i.e. the source and drain, through a body region of the opposite conductivity type. The current flows through such body region and a “lateral drift” region, in response to an applied gate voltage which creates an inversion channel in the body region, and a drain to source voltage which regulates the current which flows therein.
Generally, transistors are fabricated by placing an undoped polycrystalline material, for example polysilicon, over a relatively thin gate oxide, and implanting the polycrystalline material and adjacent active regions with an impurity dopant material to form source and drain regions. Transistors fabricated in the upper semiconductor layer of an SOI structure have multiple advantages over the transistors fabricated on conventional bulk silicon substrates. These advantages include, among others, resistance to short-channel effect, increased current drive, higher packing density, and reduced parasitic capacitance. However, despite all these attractive properties, SOI technology still has some drawbacks, which reduce the benefits of using this technology for high-performance and high-density ultra large scale integrated circuits.
One drawback of the SOI technology is the conductivity of the top semiconductor layer and its inherent floating body effect, which has particular significance for partially-depleted (PD) or non-fully depleted SOI devices. The floating body effect in such devices occurs as a result of the buried oxide that isolates the channel region of such device and allows charge carriers to build up in the channel region. In a partially-depleted FET, charge carriers (holes in an NFET and electrons in a PFET), generated by impact ionization and drain junction leakage near the drain/body region, accumulate near the source/body region of the transistor. When sufficient carriers accumulate, they are stored in the floating body, which is formed right below the channel region, and alter the floating body potential. As a result, kinks in the current/voltage (I/V) curve occur, the threshold voltage is lowered, the dynamic data retention time is altered, and the overall electrical performance of the device may be severely degraded.
One technique for diminishing the negative effects of the charge build up has been to form FETs over a fully depleted (FD) SOI substrate. For this, the upper semiconductor layer or island must be sufficiently thin so that the entire thickness of the body region is depleted of majority carriers and both junctions are at ground. Unfortunately, thin semiconductor islands are extremely costly and difficult to manufacture, due primarily to the sensitivity to variations of semiconductor film thickness and doping profile across the wafer, as well as to the large source/drain parasitic resistance. In addition, the low threshold voltage of a conventional fully depleted (FD) SOI causes large subthreshold leakage and low subthreshold voltage.
Accordingly, it is desirable to provide an improved method for fabricating an LDMOS transistor structure over a fully-depleted SOI substrate. In addition, it is desirable to provide methods for fabricating LDMOS transistor structures with components lying in and over an SOI insulator layer and with components lying in and over bulk semiconductor material. Also, it is desirable to provide improved integrated circuits including LDMOS transistor structures. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.